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Sheet目录3870

33页 34页 35页 36页 [37页]38页 39页 40页 41页

PIC18F2221/2321/4221/4321 FAMILY

DS39689F-page 32

2009 Microchip Technology Inc.

3.6

Internal Oscillator Block

The PIC18F2221/2321/4221/4321 family of devices

includes an internal oscillator block which generates

two different clock signals; either can be used as the

microcontroller’s clock source. This may eliminate the

need for external oscillator circuits on the OSC1 and/or

OSC2 pins.

The main output (INTOSC) is an 8 MHz clock source,

which can be used to directly drive the device clock. It

also drives a postscaler, which can provide a range of

clock frequencies from 31 kHz to 4 MHz. The INTOSC

output is enabled when a clock frequency from 125 kHz

to 8 MHz is selected. The INTOSC output can also be

enabled when 31 kHz is selected, depending on the

INTSRC bit (OSCTUNE<7>).

The other clock source is the internal RC oscillator

(INTRC), which provides a nominal 31 kHz output.

INTRC is enabled if it is selected as the device clock

source; it is also enabled automatically when any of the

following are enabled:

Power-up Timer

Fail-Safe Clock Monitor

Watchdog Timer

Two-Speed Start-up

These features are discussed in greater detail in

Section 24.0 “Special Features of the CPU”.

The clock source frequency (INTOSC direct, INTRC

direct or INTOSC postscaler) is selected by configuring

the IRCF bits of the OSCCON register (page 37).

3.6.1

INTIO MODES

Using the internal oscillator as the clock source elimi-

nates the need for up to two external oscillator pins,

which can then be used for digital I/O. Two distinct

configurations are available:

In INTIO1 mode, the OSC2 pin outputs FOSC/4,

while OSC1 functions as RA7 (see Figure 3-8) for

digital input and output.

In INTIO2 mode, OSC1 functions as RA7 and

OSC2 functions as RA6 (see Figure 3-9), both for

digital input and output.

FIGURE 3-8:

INTIO1 OSCILLATOR MODE

FIGURE 3-9:

INTIO2 OSCILLATOR MODE

3.6.2

INTOSC OUTPUT FREQUENCY

The internal oscillator block is calibrated at the factory

to produce an INTOSC output frequency of 8 MHz.

The INTRC oscillator operates independently of the

INTOSC source. Any changes in INTOSC across

voltage and temperature are not necessarily reflected

by changes in INTRC or vice versa.

3.6.3

OSCTUNE REGISTER

The INTOSC output has been calibrated at the

factory but can be adjusted in the user’s application.

This

done

writing

TUN<4:0>

(OSCTUNE<4:0>)

the

OSCTUNE

(Register 3-1).

When the OSCTUNE register is modified, the INTOSC

frequency will begin shifting to the new frequency.

Code execution continues during this shift. There is no

indication that the shift has occurred. The INTRC is not

affected by OSCTUNE.

The OSCTUNE register also implements the INTSRC

(OSCTUNE<7>) and PLLEN (OSCTUNE<6>) bits,

which control certain features of the internal oscillator

block. The INTSRC bit allows users to select which

internal oscillator provides the clock source when the

31 kHz frequency option is selected. This is covered in

greater detail in Section 3.7.1 “Oscillator Control

Register”.

The PLLEN bit controls the operation of the Phase

Locked Loop (PLL) in Internal Oscillator modes (see

Figure 3-10).

FIGURE 3-10:

INTOSC AND PLL BLOCK

DIAGRAM

PIC18FXXXX

OSC2

FOSC/4

I/O (OSC1)

RA7

PIC18FXXXX

I/O (OSC2)

RA6

I/O (OSC1)

RA7

VCO

Loop

Filter

OSC2

PLLEN

FIN

FOUT

SYSCLK

Phase

Comparator

8 or 4 MHz

÷4

(OSCTUNE<6>)

MUX

RA6

CLKO

INTOSC

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